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AT25F4096
to write the status register, the device must first be write enabled via the WREN instruc-
tion. Then, the instruction and data for the four bits are entered. During the internal write
cycle, all instructions will be ignored except RDSR instructions. The AT25F4096 will
automatically return to write disable state at the completion of the WRSR cycle.
Note:
When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as
long as the WP pin is held low.
Table 9. WPEN Operation
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEN
0
1
0
1
0
1
ProtectedBlocks
Protected
Protected
Protected
Protected
Protected
Protected
UnprotectedBlocks
Protected
Writable
Protected
Writable
Protected
Writable
Status Register
Protected
Writable
Protected
Protected
Protected
Writable
READ (READ): Reading the AT25F4096 via the SO (Serial Output) pin requires the fol-
lowing sequence. After the CS line is pulled low to select a device, the Read instruction
is transmitted via the SI line followed by the byte address to be read (Refer to Table 10).
Upon completion, any data on the SI line will be ignored. The data (D7-D0) at the speci-
fied address is then shifted out onto the SO line. If only one byte is to be read, the CS
line should be driven high after the data comes out. The Read instruction can be contin-
ued since the byte address is automatically incremented and data will continue to be
shifted out of the AT25F4096 until the highest address is reached, the address counter
will roll over to the lowest address allowing the entire memory to be read in one continu-
ous Read instruction.
PROGRAM (PROGRAM): In order to program the AT25F4096, two separate instruc-
tions must be executed. First, the device must be write enabled via the WREN
instruction. Then the Program instruction can be executed. Also, the address of the
memory location(s) to be programmed must be outside the protected address field loca-
tion selected by the block write protection level. During an internal self-timed
programming cycle, all commands will be ignored except the RDSR instruction.
The Program instruction requires the following sequence. After the CS line is pulled low
to select the device, the Program instruction is transmitted via the SI line followed by the
byte address and the data (D7-D0) to be programmed (Refer to Table 6). Programming
will start after the CS pin is brought high. The low-to-high transition of the CS pin must
occur during the SCK low time immediately after clocking in the D0 (LSB) data bit.
The Ready/Busy status of the device can be determined by initiating a RDSR instruc-
tion. If Bit 0 = “1”, the program cycle is still in progress. If Bit 0 = “0”, the program cycle
has ended. Only the RDSR instruction is enabled during the program cycle.
A single Program instruction programs 1 to 256 consecutive bytes within a page if it is
not write protected. The starting byte could be anywhere within the page. When the end
of the page is reached, the address will wrap around to the beginning of the same page.
If the data to be programmed are less than a full page, the data of all other bytes on the
same page will remain unchanged. If more than 256 bytes of data are provided, the
address counter will roll over on the same page and the previous data provided will be
replaced. The same byte cannot be reprogrammed without erasing the whole sector
9
2454G–SFLSH–5/06
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